Maiesha Fahomida, Nushraq Nawer Hossain, Farhan Ahmad Nafis, Raian Islam
Modern digital communication requires stronger mechanisms for both confidentiality and authentication to mitigate threats such as impersonation, replay, and eavesdropping. Although traditional cryptographic methods offer secrecy, they lack strong identity verification in adversarial environments. To ensure security in both transmission and authentication, we proposed a hybrid framework combining the most effective mechanisms for secure communication, enhanced with LSB Steganography to conceal sensitive information. Zero-knowledge proofs are used for secure authentication. Diffie-Hellman with AES-256-GCM ensures confidentiality and data integrity, while LSB Steganography provides secure concealment of transmitted communication. Our method has been evaluated using a variety of techniques, including steganographic quality assessment, encryption-decryption performance testing, and authentication time measurement, confirming its resilience against common security risks. The proposed methods achieve PSNR values up to$\mathbf{7 4. 5 8 ~ d B}$and SSIM of 0.9999. The encryption time ranges from 0.035 ms to 0.068 ms, while the decryption time remains consistently lower, ranging from 0.008 ms to 0.015 ms. The results demonstrate that the proposed framework is a viable option for secure data transfer, as it guarantees confidentiality, integrity, authentication, and covert communication.
Jiahao Li, Qiang Liu, Ray C.C. CHEUNG, Zhaohui Guo
Zero-Knowledge Proof (ZKP) has been widely applied in fields such as blockchain and privacy-preserving computing. However, the proof generation process remains computationally complex and time-consuming, which limits its further applications. Various schemes have been proposed to optimize the underlying modular operations with dedicated hardware support, but existing schemes still face low-efficiency problems. To address the problems, we propose an efficient Barrett modular multiplier design, especially for ZKP. Evaluation on a Xilinx XCVU9P FPGA shows that, compared to two existing pipelined designs, the proposed design improves throughput per slice by up to 20.4% and 49.6%, respectively, and achieves an $8.6 \times$ improvement over an existing non-pipelined design.
Code-based group signatures are a promising candidate for post-quantum cryptography, but existing code-based group signature schemes struggle with the challenges of large signature sizes caused by zero-knowledge proofs. To address this issue, we propose a novel and practical code-based group signature scheme built upon the Schnorr-Lyubashevsky paradigm. Our construction achieves constant-size signatures and public keys, independent of the group cardinality, and its security is formally proven in the random oracle model under the hardness assumptions of the Syndrome Decoding (SD) and Decoding One Out of Many (DOOM) problems. To alleviate the performance bottleneck of rejection sampling, we design and implement a batch processing optimization for the signing algorithm, which significantly accelerates signature generation by applying vectorization to the most computationally intensive operations. Experimental results show that the optimization renders signing practical. Our scheme features the most compact signature size among existing codebased group signature schemes. All related code is open-sourced and available at https://github.com/Latters/CodeBasedGroupSig/.
The growth of cloud computing in the healthcare field has led to significant developments, but ensuring the confidentiality and protection of medical records such as electronic health records (EHRs) remains a major concern for healthcare service applications. In cloud computing, the basic authentication provided by most service providers is insufficient to ensure secure access to critical or sensitive resources. Moreover, most of the existing healthcare management systems are ineffective in handling a number of patient data, which leads to single points of failure. To address these issues, elliptic curve cryptography (ECC) with Curve25519 is utilized to enhance security in cloud storage, particularly within healthcare management systems. The ECC with Curve25519 is optimized for efficient and fast scalar multiplication, which reduces computational overhead and enhances performance. The curve parameters are selected to prevent vulnerabilities and ensure security against known attacks. Moreover, it is efficient in maintaining the integrity of patient records, which reduces storage and bandwidth requirements. The ECC with Curve25519 achieves lower Key-Gen, prove, verify, proving key size, and verification key size of 13.7 s, 48 s, 0.608 s, 13.27 Mb, and 123.70 Kb, respectively, in comparison with proxy re-encryption algorithm with zero-knowledge proof (ZKP).
Zero-knowledge proofs (ZKPs) enable a prover to convince a verifier of knowledge of a secret without revealing it. The ZKP for the square-root problem has many applications in network and cloud security, such as user authentication and privacy-preserving cloud storage auditing. Classical protocols for the quadratic residuosity (square-root) relation require multiple iterations to reach negligible soundness error, incurring latency and communication costs that are critical in cloud settings. This paper proposes a new single-round zero-knowledge proof (SR-ZKP) for the square-root problem that achieves the same soundness as iterative schemes by increasing the challenge length. The protocol requires only one execution of a 4-message protocol (request, commit, challenge, response) and can be transformed into a one-message non-interactive ZKP via the Fiat–Shamir heuristic. The completeness, soundness, and zero-knowledge properties of the proposed scheme are formally proven. The results of this study show that the proposed protocol can achieve approximately \(97\%\) reduction in communication overhead and latency, when compared to an 80-round iterative ZKPs with RSA modulus n of size 2048 bits. This provides a substantial advantage for cloud applications.
A Modular DSP Architecture for Extreme-Precision Computation of π Author: José Ignacio Peinador SalaContact: joseignacio.peinador@gmail.comORCID: 0009-0008-1822-3452 🎯 TL;DR: What's This About? Problem: Calculating π at extreme precision hits a "Memory Wall" — parallel algorithms choke on shared memory access. Breakthrough: We discovered that π's calculation can be decomposed using modular arithmetic (mod 6), creating 6 independent computation channels with zero inter-thread communication. Key Insight: This decomposition is grounded in a formal isomorphism with polyphase filter banks in Digital Signal Processing (DSP), a bridge between number theory and engineering established in our companion work. Result: ✅ 100 million digits of π computed with just 6.8 GB RAM (95% parallelisation efficiency) ✅ Shared-Nothing architecture with strictly isolated memory per channel ✅ Stride-6 transition leaf with exact phase correction, compressing recursion depth by 2.6× ✅ Open-source implementation in Python/gmpy2, executable on Google Colab's free tier Why it matters: This architecture transforms an intrinsically memory-bound problem into a CPU-bound one, enabling near-linear scaling on commodity hardware without specialised HPC infrastructure. 📖 Executive Summary This repository hosts the reference implementation and experimental validation of the Hybrid Stride-6 architecture for extreme-precision computation of π. The architecture exploits the arithmetic structure of the Chudnovsky series by decomposing it into six independent modular channels, each processed by a dedicated worker with its own memory space. The decomposition is not an ad hoc optimisation but rests on a rigorous mathematical foundation: the polyphase isomorphism between modular arithmetic on ℤ/6ℤ and multirate signal processing. This isomorphism guarantees perfect reconstruction (no information loss across channels) and orthogonality (no inter-channel interference). The architecture is validated through the 100M Barrier Run: computing 10⁸ digits of π on a resource-constrained Google Colab instance (2 vCPUs, 12 GB RAM) in under 20 minutes, with 95% parallelisation efficiency and a sustained throughput of over 83,000 digits per second. 🏆 Key Contributions 🔬 Theoretical Foundations (Summarised from Companion Work) Polyphase Isomorphism: Formal proof that modular decomposition of integer-indexed series is equivalent to polyphase decimation in DSP Hexagonal Lattice Connection: Geometric motivation via the A₂ lattice (densest circle packing in the plane) Perfect Reconstruction Guarantee: Mathematical proof that the six channels recombine without aliasing or leakage ⚡ Computational Architecture Shared-Nothing Design: Six independent Python processes with strictly isolated memory spaces Stride-6 Transition Leaf: Processes blocks of 6 consecutive terms in a single operation, reducing recursion tree depth by log₂6 ≈ 2.585 Critical Phase Correction: Direct accumulation of the linear term B(k) prevents off-by-one-stride phase errors 📊 Experimental Validation 100M Barrier Run: 100 million digits computed on 12 GB RAM with 95% parallel efficiency Orthogonality Verification: ℓ² norm of channel terms matches norm of original series to machine precision Reference Comparison: All 10⁸ digits match y-cruncher reference values exactly 📈 Performance Highlights 🚀 "The 100M Barrier Run" — Extreme Validation Metric Result Significance Digits Calculated 100,000,000 Exascale-capable architecture Total Time 1,194.32 s (19.90 min) Sustained performance on cloud hardware Parallel Efficiency 95% (1.90× speedup) Near-linear scaling on 2 cores Peak RAM Usage ~6.8 GB Runs within 12 GB Colab limit Throughput 83,729 digits/second Competitive with optimised implementations Numerical Integrity Bit-exact match with y-cruncher Zero cumulative error 🏗️ Architectural Comparison Aspect Monolithic Binary Splitting Hybrid Stride-6 (This Work) y-cruncher (State-of-Art) Memory Pattern Contiguous, saturates bus Local per core, optimises cache Sequential disk I/O Parallel Model Fine-grained synchronisation Embarrassingly parallel (6 processes) Optimised with locks Scalability Memory-bound CPU-bound, linear to 6 cores Disk-speed limited RAM Requirement Entire dataset in memory Working set reduced 6× Uses disk as RAM Design Philosophy Maximise single-thread speed Maximise resource efficiency Maximise absolute speed 🚀 Quick Start & Reproduction 1. Instant Online Experiment (Recommended) Click above to run the complete experimental validation in Google Colab — no installation required! 2. Key Experiments to Reproduce The companion notebook provides step-by-step reproduction of all manuscript claims: Theoretical Foundation: Verify the polyphase decomposition and energy conservation Stride-6 Algorithm: Test parallel computation with arbitrary precision (100k digits) 100M Barrier Run: Reproduce the full-scale benchmark (requires ~7 GB RAM) Performance Analysis: Measure speedup and parallel efficiency ⚙️ Technical Implementation Details The "Stride-6" Computational Engine Unlike conventional Binary Splitting (processes terms individually), our engine implements a compressed transition leaf that calculates the aggregate effect of 6 consecutive terms: def stride6_leaf(k_start): """Calculate compressed transition for block [k, k+5]""" P, Q, B_acc = 1, 1, 0 for m in range(6): n = k_start + m P_n, Q_n, B_n = compute_chudnovsky_term(n) P *= P_n Q *= Q_n B_acc += B_n # Critical phase accumulation T_leaf = Q * B_acc # Correct phase synthesis return P, Q, T_leaf Key Innovation: Direct accumulation of the linear term B(n) prevents phase drift, preserving arithmetic integrity at any scale. Shared-Nothing Architecture Each of the 6 workers operates in complete memory isolation: Independent address spaces (no shared memory locks) Local garbage collection (prevents heap fragmentation) Cache-optimised access patterns (maximises L1/L2 utilisation) Numerical Stability Guarantees Orthogonal decomposition — zero information loss (verified experimentally) Arbitrary precision backend (gmpy2) with proven numerical stability Exact phase correction in the Stride-6 leaf 📚 Citation & Academic Use If this work contributes to your research, please cite: @article{peinador2026modularDSP, title={A Modular DSP Architecture for Extreme-Precision Computation of π}, author={Peinador Sala, José Ignacio}, journal={Zenodo}, year={2026}, doi = {10.5281/zenodo.17768718}, url = {https://github.com/NachoPeinador/Arquitectura-de-Hibridacion-Algoritmica-en-Z-6Z} } The companion theoretical work establishing the polyphase isomorphism is: @article{peinador2026polyphase, title={Polyphase Isomorphism between Modular Arithmetic and Multirate Signal Processing}, author={Peinador Sala, José Ignacio}, year={2026}, publisher={Zenodo}, doi = {10.5281/zenodo.17680023} } 🌐 The Broader Research Programme This architecture is one component of a larger investigation into the computational and physical consequences of the ℤ/6ℤ modular symmetry. Related projects include: Polyphase Isomorphism: Formal mathematical proof of the isomorphism between modular arithmetic and DSP. Modular Substrate Theory: Unified framework for cosmology and hadronic physics. Topological State Preparation: Quantum register initialisation and dissipative protection via ℤ/6ℤ superselection. Common Thread: All projects leverage modular arithmetic (ℤ/6ℤ) as a fundamental organising principle across mathematics, physics, and computation. ⚖️ Licensing & Usage ✅ Academic & Research Use (Free) Available under PolyForm Noncommercial License 1.0.0: Permitted: Academic research, teaching, personal projects, non-commercial forks Requirements: Attribution, license preservation, non-commercial use ⛔ Commercial Use (License Required) Commercial applications require explicit permission, including: Integration into proprietary software products Commercial hardware benchmarking services SaaS platforms and cloud computing services 💼 For Commercial Licensing Inquiries:Contact: joseignacio.peinador@gmail.comSubject: "Commercial License Inquiry — Modular π Architecture" 🌟 Acknowledgments This independent research was enabled by: Infrastructure & Tools Google Colab for democratised computational resources Python ecosystem (gmpy2, NumPy, SciPy, Jupyter) for scientific computing GitHub for open collaboration infrastructure Data & References y-cruncher for validation benchmarks Digital Signal Processing community for foundational theory Community & Inspiration The open-source scientific community for collective knowledge advancement Independent researchers worldwide pushing boundaries outside traditional institutions Last updated: June 2026 | Version: 3.0 | Status: Actively Maintained
We present ZK IR, a novel 32-bit instruction set architecture (ISA) specifically designed for efficient zero-knowledge proof generation using STARK protocols. Unlike existing zkVMs that adapt general-purpose ISAs like RISC-V, ZK IR is designed from first principles to minimize proving overhead while maintaining compatibility with modern compiler toolchains. Our key contribution is a rigorous analysis demonstrating that a pure 32-bit register architecture with software-based multi-precision arithmetic outperforms designs with wider registers or specialized field arithmetic units. We achieve approximately 2× reduction in constraint count compared to naive approaches. ZK IR uses the Baby Bear field (31-bit prime) with Plonky3 for proving, and provides an LLVM-based compiler infrastructure enabling developers to write ZK applications in Rust, C, and C++.
Hikaru Okamoto, Vu Trung Duong Le, Hoai Luan Pham, Van Tinh Nguyen · 5 authors
Zero-Knowledge Proof (ZKP) is a privacy-preserving protocol that allows a prover to demonstrate the validity of a statement without revealing its details. A widely used primitive of ZKP, Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (zk-SNARK), has attracted significant attention in edge computing; however, edge devices face severe resource constraints when processing its computational bottleneck, Montgomery multiplication. This paper proposes MMzk, a lightweight hardware architecture optimized for 384-bit Coarsely Integrated Operand Scanning (CIOS) Montgomery multiplication, which is primarily employed in multi-scalar multiplication (MSM) of zk-SNARKs. To achieve both high performance and resource efficiency, MMzk core operating at the System-on-Chip (SoC) level integrates three key optimizations: resource sharing of two adders, a subtractor, and a multiplier; effective memory organization for large-data processing; and double-buffering memory scheduling. Implementation results on a Xilinx ZCU102 SoC show that MMzk core operates at up to 250MHz with a utilization of 3,590 LUTs, 1,648 FFs, 16 DSPs, and 6 BRAM36 blocks. Compared with existing FPGA-based counterparts, it achieves a throughput of 657.53Mbps (up to 35.9 times higher) and an area efficiency of 81.48Kbps/eLUT (up to 9.5 times higher). Furthermore, real-time evaluation demonstrates an energy efficiency of 9,030Mbps/W at 250MHz and 67mW, surpassing modern CPUs by up to 52.9 times. These results confirm MMzk core as an energy-efficient and high-performance solution for zk-SNARK-based blockchain systems and other Montgomery multiplication applications.
Verifiable Random Functions (VRFs) and Oblivious Pseudorandom Functions (OPRFs) are essential cryptographic primitives in privacy-preserving applications such as anonymous authentication, private set intersection (PSI), and decentralized identity. Existing constructions, however, rely on number-theoretic assumptions that are vulnerable to quantum attacks. This PhD research project focuses on constructing efficient and practical VRFs and OPRFs from lattice-based assumptions to ensure post-quantum security. A key obstacle in these constructions is the overhead of zero-knowledge proofs (ZKPs), particularly range proofs, which are costly in terms of size and prover complexity. To address this, we investigate probabilistic techniques that relax exact correctness. In particular, we explore approximate range proofs and algebraic transformations, such as using automorphisms in polynomial rings to simulate inner product arguments via polynomial multiplication. These methods enable more efficient and scalable lattice-based constructions of VRFs, including group and context-bound variants, as well as OPRFs. The goal is to make these primitives practical for deployment in post-quantum privacy-preserving systems.
Sangwon Shin, Ngoc-Son Pham, Lei Xu, Weidong Shi · 5 authors
Zero-Knowledge Proof (ZKP) cryptographic algorithms have garnered significant attention for their ability to enhance privacy. However, the practical deployment of these algorithms remains challenging because they demand extremely high computational effort and handle huge volumes of data, especially in the Number Theoretic Transform (NTT) step. In this work, we propose an HBM-aware dataflow that employs sub-tiling and row-shuffling techniques to overcome the nonuniform stride access problem and to maximize HBM bandwidth utilization. We also design the NTT accelerator to use minimal FPGA resources. In particular, we explore diverse design options for the 256-bit modular multiplier and adopt an efficient design that optimizes resource usage and performance. Experimental results demonstrate that the proposed accelerator achieves lower latency and enhanced resource utilization compared to state-of-the-art FPGA-based designs.
List decoding of codes can be seen as the generalization of unique decoding of codes while list decoding over finite fields has been extensively studied, extending these results to more general algebraic structures such as Galois rings remains an important challenge. Due to recent progress in zero knowledge systems, there is a growing demand to investigate the proximity gap of codes over Galois rings in Yizhou Yao(2025). The proximity gap is closely related to the decoding capability of codes. It was shown in Eli Ben-Sasson(2020) that the proximity gap for RS codes over finite field can be improved to $1-\sqrt{r}$ if one consider list decoding instead of unique decoding. However, we know very little about RS codes over Galois ring which might hinder the development of zero knowledge proof system for ring-based arithmetic circuit. In this work, we first extend the list decoding procedure of Guruswami and Sudan to Reed-Solomon codes over Galois rings, which shows that RS codes with rate $r$ can be list decoded up to radius $1-\sqrt{r}$. Then, we investigate the list decoding of folded Reed-Solomon codes over Galois rings. We show that the list decoding radius of folded Reed-Solomon codes can reach the Singlton bound as its counterpart over finite field. We also extend the deterministic pruning method of Vikrant Ashvinkumar(2026) to Galois rings, showing how to prune the affine free module obtained from the linear-algebraic decoder and recover the candidate codewords. Finally, we improve the list size of our folded Reed-Solomon code to $O(1/\varepsilon^2)$ by extending recent work in Shashank Srivastava(2025) to Galois Rings. By developing the recent work of Yeyuan Chen(2025), we show that folded Reed-Solomon codes over Galois rings satisfy the relaxed generalized Singleton bound in the average-radius sense with optimal list size $O(1/\varepsilon)$.
Barrett's algorithm is one of the most widely used methods for performing modular multiplication, a critical nonlinear operation in modern privacy computing techniques such as homomorphic encryption (HE) and zero-knowledge proofs (ZKP). Since modular multiplication dominates the processing time in these applications, computational complexity and memory limitations significantly impact performance. Computing-in-Memory (CiM) is a promising approach to tackle this problem. However, existing schemes currently suffer from two main problems: 1) Most works focus on low bit-width modular multiplication, which is inadequate for mainstream cryptographic algorithms such as elliptic curve cryptography (ECC) and the RSA algorithm, both of which require high bit-width operations; 2) Recent efforts targeting large number modular multiplication rely on inefficient in-memory logic operations, resulting in high scaling costs for larger bit-widths and increased latency. To address these issues, we propose LaMoS, an efficient SRAM-based CiM design for large-number modular multiplication, offering high scalability and area efficiency. First, we analyze the Barrett's modular multiplication method and map the workload onto SRAM CiM macros for high bit-width cases. Additionally, we develop an efficient CiM architecture and dataflow to optimize large-number modular multiplication. Finally, we refine the mapping scheme for better scalability in high bit-width scenarios using workload grouping. Experimental results show that LaMoS achieves a $7.02\times$ speedup and reduces high bit-width scaling costs compared to existing SRAM-based CiM designs.
Dingsen Shi, Chris Tsu, Ying He, Alex Goss · 8 authors
Zero-Knowledge Proofs (ZKPs) are becoming a foundational technology for scalable and privacy-preserving blockchain systems, especially through applications like zkRollups. However, the computational intensity of proof generation continues to limit real-world deployment. We present ZKPU, a hardware-software co-designed ZK accelerator that combines native NVMe integration—ensuring seamless compatibility across existing server and edge infrastructure—with a modular RISC-V System-on-Chip (SoC) architecture that opens the path to eliminating host–device communication bottlenecks. ZKPU is designed to flexibly support a wide range of ZK workloads; in this work, we demonstrate its capabilities by implementing and optimizing multi-scalar multiplication (MSM), a core bottleneck in many zk-SNARK systems. Built using the Chipyard framework and equipped with dedicated modular arithmetic units, ZKPU achieves significant performance and energy efficiency improvements over CPU, GPU, and FPGA baselines. Our results highlight ZKPU as a practical and forward-compatible foundation for scalable ZK acceleration in modern decentralized systems.
Driven by the increasing demand for multi-party data computation, Private Set Intersection (PSI) has become a pivotal technique for secure data sharing and privacy preservation. Although several efficient two-party PSI protocols have been developed, multi-party scenarios continue to suffer from limited computational efficiency and inadequate security guarantees. To address this engineering challenge, this study aims to enhance the performance and security of multi-party PSI protocols. We introduce SM-MPSI, a multi-party PSI protocol built upon national cryptographic standards. This protocol integrates SM2 and SM3 cryptographic mechanisms, employs non-interactive zero-knowledge proofs for identity authentication, and leverages domestic secure cryptographic chips to accelerate core algorithms. Experimental comparisons with existing mainstream protocols demonstrate significant improvements in computational efficiency and system scalability, while preserving robust security guarantees. Furthermore, SM-MPSI achieves enhanced communication efficiency and reduced resource consumption in multi-party scenarios. This research offers technical contributions toward advancing China's efforts in independent innovation in privacy-preserving computing and cryptographic technologies, thereby laying a solid foundation for strengthening national cybersecurity capabilities.
This paper addresses the challenge of designing secure and private digital credentialing systems by leveraging advanced mathematical primitives from applied cryptography. The core of our proposed solution is the application of Zero-Knowledge Proofs (ZKPs), a class of cryptographic protocols that allows for the verification of assertions without disclosing the underlying secret data. We introduce a formal, layered architecture that demonstrates how the mathematical properties of ZKPs can be systematically translated into a robust, large-scale information system. The framework's design is validated against the complex requirements of the academic domain, which serves as a rigorous testbed for our architectural approach. The primary contribution is a blueprint for integrating complex cryptographic protocols into practical system design, demonstrating how mathematical guarantees of privacy can be preserved in a distributed and verifiable manner. This work provides a novel contribution at the intersection of applied cryptography, system architecture, and information security.
A polynomial commitment scheme (PCS) enables a prover to commit to a polynomial and later prove the correctness of its evaluation without revealing the polynomial. Although discrete logarithm-based PCSs offer succinct proofs, they are not quantum-safe. Lattice-based PCSs provide post-quantum security and additive homomorphism, making them suitable for applications such as zero-knowledge proofs and secure multiparty computation. In this article, we review two recent lattice-based PCSs, Greyhound and HyperWolf, both relying on the Module-SIS assumption but differing in target polynomial classes and proof techniques. In particular, Greyhound achieves a smaller proof size O(log log N) through folding and LaBRADOR proofs, while HyperWolf supports univariate and multilinear polynomials with lower verifier cost O(log N) using hypercube evaluation.