HBM-Aware Number Theoretic Transform Accelerator for Zero-Knowledge Proof

Abstract

Zero-Knowledge Proof (ZKP) cryptographic algorithms have garnered significant attention for their ability to enhance privacy. However, the practical deployment of these algorithms remains challenging because they demand extremely high computational effort and handle huge volumes of data, especially in the Number Theoretic Transform (NTT) step. In this work, we propose an HBM-aware dataflow that employs sub-tiling and row-shuffling techniques to overcome the nonuniform stride access problem and to maximize HBM bandwidth utilization. We also design the NTT accelerator to use minimal FPGA resources. In particular, we explore diverse design options for the 256-bit modular multiplier and adopt an efficient design that optimizes resource usage and performance. Experimental results demonstrate that the proposed accelerator achieves lower latency and enhanced resource utilization compared to state-of-the-art FPGA-based designs.