For better or worse, non-fungible tokens (NFTs) are the most peculiar and least expected art market innovations of the early twenty-first century. This chapter provides a brief history of NFTs and the NFT market, beginning with the invention of blockchain technology, through the creation of the Bitcoin, Namecoin, and Ethereum blockchains, and the NFT phenomenon. It describes a selection of NFT projects and artists and provides a theoretical account of both the art market and the NFT market.
Physical Unclonable Functions (PUFs) and Hardware Security
Maximal Extractable Value (MEV) represents a pivotal challenge within the Ethereum ecosystem; it impacts the fairness, security, and efficiency of both Layer 1 (L1) and Layer 2 (L2) networks. MEV arises when miners or validators manipulate transaction ordering to extract additional value, often at the expense of other network participants. This not only affects user experience by introducing unpredictability and potential financial losses but also threatens the underlying principles of decentralization and trust. Given the growing complexity of blockchain applications, particularly with the increase of Decentralized Finance (DeFi) protocols, addressing MEV is crucial. This paper presents a comprehensive survey of MEV mitigation techniques as applied to both Ethereums L1 and various L2 solutions. We provide a novel categorization of mitigation strategies; we also describe the challenges, ranging from transaction sequencing and cryptographic methods to reconfiguring decentralized applications (DApps) to reduce front-running opportunities. We investigate their effectiveness, implementation challenges, and impact on network performance. By synthesizing current research, real-world applications, and emerging trends, this paper aims to provide a detailed roadmap for researchers, developers, and policymakers to understand and combat MEV in an evolving blockchain landscape.
Intelligent management of power flow and storage balance has proven its worth in supporting economic, sustainable operation of microgrids powered mainly by intermittent renewable energy resources. In particular, the introduction of Multi-Agent Reinforcement Learning (MARL) to solve power management and storage balance problems has been very successful. MARL primary-secondary control was the subject of a recent application in solving power storage flow problems in battery-based micro- and smart-grids, focusing upon vehicle-to-grid applications under realistic environmental considerations such as infrastructural influences. Such influences can worsen the accuracy of plug-and-play batteries' charge-discharge synchronization and hence control stabilization, power flow balance, batteries' health/life, and energy efficiency. This paper proposes a solution to this issue in a DC autonomous microgrid with multiple, heterogeneous batteries. Multiagent-neighbor-to-neighbor information is exploited to enhance the real-time balance of the load participation, and a real-time decentralized infrastructure compensation and power flow organization consumption/loss is established to compensate for infrastructural/environmental influence on the control. Moreover, implementation in a real-time economic sustainable participation policy on each BESS in a test microgrid is explored. The results verify improved synchronization of the batteriesâ power flow with reduced plug-and-play time by (4.16%), enhanced output voltage balance by (2.76-8%), reduced power consumption by (1.908-2.94%), improved power flow balance by (2.765-6.486%), and better power flow efficiency by (0.9196-2.626%) when compared to a baseline MARL implementation.
Jieyu Li, Weifeng He, Bo Zhang, Guanghui He ¡ 7 authors
This article presents a timing slack inference and clock frequency adaption technique, named TICA, to mitigate the large and pessimistic timing guardband reserved for process, voltage, and temperature (PVT) variations in deeply pipelined ultra-low-voltage (ULV) circuits. TICA can perceive the dynamic PVT variations of a circuit with in situ cycle borrowing detectors, then infer its runtime timing slack, and adjust the clock frequency accordingly to minimize the redundant timing margin timely. Therefore, with TICA, a circuit can maintain a small amount of positive timing slack, free from the costly timing error correction process required in conventional in situ timing error detection and correction (EDAC)-based circuits. For error-tolerant applications, TICA can also keep the circuitâs timing slack at a small negative level for further energy efficiency and throughput improvements. Moreover, an inference-accuracy-driven in situ cycle borrowing detector insertion method is presented, which greatly reduces the insertion rate and the associated timing error detection overheads by leveraging the monotonic relationship between the timing slack and the number of cycle borrowing events. We implement TICA in a near-threshold-voltage (NTV) bitcoin mining core featuring a 64-stage deeply pipelined SHA256 engine in a 28-nm process, with only 0.59% in situ detector insertion rate and 1.4% area overhead. Silicon measurements show$4.2\times $throughput improvements or 19.3% energy savings without any timing error compared to the baseline margined for a 10%$V_{\mathrm {DD}}$drop, as well as additional 35.7% throughput gains or 10.6% energy savings at 0.3 V when maintaining the error rate of SHA256 computing results at 1%.
Low-power high-performance VLSI design
Semiconductor materials and devices
Advancements in Semiconductor Devices and Circuit Design
Jieyu Li, Weifeng He, Bo Zhang, Guanghui He ¡ 6 authors
Energy-efficient bitcoin mining cores have gained significant attention since the energy cost for computing dominates the mining expenses [1]. Ultra-low-voltage (ULV) digital circuits have emerged as an attractive approach to improve the energy-efficiency. However, they demand a large timing margin for the worst-case process, voltage, and temperature (PVT) variations, undermining a significant portion of energy savings. Recent works, including multi-phase latch pipeline [1], tunable replica circuits [2]â[3], in-situ error detection and correction (EDAC) [4]â[6], and dynamic timing enhancement [7], can reduce the pessimistic margin. However, it is not straightforward to adopt those techniques in mining cores due to their deeply-pipelined architecture (up to 128 stages [1]). For example, to adopt EDAC, the deep pipeline requires inserting many bulky error detectors as it has many critical paths. Our experiment with a 0.3V 28-nm mining core shows >18.9% registers need to be replaced with error detectors, considering 6Ď local process variation only. Also, multiple stages can have timing errors simultaneously, making an error correction process (e.g., clock gating [5], VDD boosting [6]) complex and costly.
Low-power high-performance VLSI design
Semiconductor materials and devices
Advancements in Semiconductor Devices and Circuit Design
Abstract Existing models for non-interactive MPC cannot provide full privacy for inputs, because they inherently leak the residual function (i.e., the output of the function on the honest partiesâ input together with all possible values of the adversarial inputs). For example, in any non-interactive sealed-bid auction, the last bidder can figure out what was the highest previous bid. We present a new MPC model which avoids this privacy leak. To achieve this, we utilize a blockchain in a novel way, incorporating smart contracts and arbitrary parties that can be incentivized to perform computation (âbounty hunters,â akin to miners). Security is maintained under a monetary assumption about the parties: an honest party can temporarily supply a recoverable collateral of value higher than the computational cost an adversary can expend. We thus construct non-interactive MPC protocols with strong security guarantees (full security, no residual leakage) in the short term. Over time, as the adversary can invest more and more computational resources, the security guarantee decays. Thus, our model, which we call Gage MPC, is suitable for secure computation with limited-time secrecy, such as auctions. A key ingredient in our protocols is a primitive we call âGage Time Capsulesâ (GaTC): a time capsule that allows a party to commit to a value that others are able to reveal but only at a designated computational cost. A GaTC allows a party to commit to a value together with a monetary collateral. If the original party properly opens the GaTC, it can recover the collateral. Otherwise, the collateral is used to incentivize bounty hunters to open the GaTC. This primitive is used to ensure completion of Gage MPC protocols on the desired inputs. As a requisite tool (of independent interest), we present a generalization of garbled circuit that are more robust: they can tolerate exposure of extra input labels. This is in contrast to Yaoâs garbled circuits, whose secrecy breaks down if even a single extra label is exposed. Finally, we present a proof-of-concept implementation of a special case of our construction, yielding an auction functionality over an Ethereum-like blockchain.
Area selective deposition via atomic layer deposition (ALD) has proven its utility in elementary nanopatterning processes. In the case of complex 3D patterned substrates, selective deposition processes lead to vertical sidewall coverage only, or top and bottom horizontal surface coverage only, to enable advanced nanopatterning and further miniaturization of microelectronic devices. While many fabrication strategies for vertical only Topographically Selective Deposition (TSD) have already been developed, the horizontal TSD case needs further attention. In this work, we propose a versatile route for the TSD on 3D top and bottom horizontal surfaces along with a proof-of-concept for such selective Ta2O5 thin film deposition. The strategy at stake relies on a plasma enhanced atomic layer deposition process assisted by energetic ion bombardment during the plasma step and followed by a postgrowth wet etching step. The effectiveness of this strategy is based on a careful adjustment of processing temperatures purposely set at low temperature, most probably below the ALD temperature window. Anisotropic ion bombardment via substrate biasing during the plasma step provides an extra amount of thermal energy only to exposed horizontal surfaces, which in turn enables a selective densification of the thin film under growth. The difference in thin film density on horizontal and vertical surfaces enables the property-selective etching of vertical surfaces, generating horizontal TSD. A proof-of-concept for such low temperature TSD is shown in the case of 3D trenched substrates with an aspect ratio of 14.
It is crucial that smart contracts are tested thoroughly due to their immutable nature. Even small bugs in smart contracts can lead to huge monetary losses. However, testing is not enough; it is also important to ensure the quality and completeness of the tests. There are already several approaches that tackle this challenge with mutation testing, but their effectiveness is questionable since they only considered small contract samples. Hence, we evaluate the quality of smart contract mutation testing at scale. We choose the most promising of the existing (smart contract specific) mutation operators, analyse their effectiveness in terms of killability and highlight severe vulnerabilities that can be injected with the mutations. Moreover, we improve the existing mutation methods by introducing a novel killing condition that is able to detect a deviation in the gas consumption, i.e., in the monetary value that is required to perform transactions. This paper has a replication package at https://github.com/pieterhartel/Mutation-at-scale
This paper presents an all-passive negative feedback network to perform autonomous RF front-end beam-forming towards the direction of the incident RF beam. The beam-forming front-end block consists of a passive network for RF signal processing, voltage rectifiers, and voltage-controlled phase shifters, all of which are passive components and consume zero DC power. A proof-of-concept 4-element self-steering beam-forming block at 5GHz is implemented in a standard 130nm CMOS process and occupies an area of 4.1mm2. The measurements demonstrate that a high-quality 4-element array factor is successfully synthesized for the input progressive phase shift from -120° to +120°. At an input power Pin of -17dBm/element, the normalized array factor is -4.3dB/-3.2dB at +90°/-90° input progressive phase shift in the closed-loop operation, out-performing reported active self-steering beam-formers. To the best of our knowledge, this is the first demonstration of an all-passive network for front-end self-steering beam-forming with zero DC power.