Blockchain Papers

Zihang Guo, Q Liu, Ray C.C. Cheung, Zhaohui Guo

No abstract is available for this record.

Leo Noel, Thomas Plantard

No abstract is available for this record.

Nobuki Fujimoto, Rei (Rei-AIOS autonomous research substrate), claude-opus-4-7) Claude (Anthropic

We present a synthesis-friendly Verilog implementation of the D-FUMT₈ Arithmetic Logic Unit, programmed onto two distinct Sipeed silicon families: Tang Console 138K (GW5AST-138B, LittleBee5 A revision, IDCODE 0x0001081B) and Tang Nano 9K (GW1NR-9C, LittleBee1 C revision, IDCODE 0x1100481B). The ALU realizes eight discrete logic values — FALSE, TRUE, NEITHER, BOTH, ZERO, FLOWING, SELF, INFINITY — encoded in 3 bits with a tier-respecting layout. The 10 supported operations include four classical-tier unary ops (NOT, OMEGA, PHI, PSI), Belnap-extended binary lattice meet/join (AND, OR), generic XOR, hardware reset, no-op, and a novel ADIABATIC operation realizing the SELF⟲ (self-reflexive) primitive: ADIABATIC(SELF) = SELF, identity elsewhere. v0.6 contributions (2026-05-10): (1) **Four-substrate cross-verification complete**: 2 Sipeed silicon families (Tang Console 138K + Tang Nano 9K, **both running byte-for-byte same dfumt8_alu_synth.v 138-line Verilog with bit-identical 0 changes to ALU logic** — only wrapper top module re-targeted for clock divider, LED polarity, and pin assignments) + Qiskit Aer simulator (Phase 1-5: 231/231 entries) + IBM Heron r2 real quantum hardware (Phase 1+2+3+5: 144/144 entries, avg fidelity 0.954). (2) **chip-portability evidence (new finding F10)**: a synthesis bug or vendor-specific assumption would diverge between LittleBee5 (5nm-class GW5AST-138B) and LittleBee1 (28nm-class GW1NR-9C) Gowin architectures; absence of divergence is operational evidence of correct synthesis on both. (3) **Tang Nano 9K User Codes**: 0x0000A5F4 (LED Blinky STEP 1038) + 0x00001D46 (D-FUMT₈ ALU STEP 1039). (4) **Reproducibility entry-cost lowered**: minimum reproduction path is ~$20 (Tang Nano 9K from 秋月電子 g117448 at ¥2,980) + free Gowin EDA Education / OSS toolchain + free Aer + free IBM Quantum Open Plan. (5) **v0.5 corrigendum RESOLVED**: Tang Nano 9K is now physical silicon programming target on equal footing with Tang Console 138K (was computational evidence only at v0.5). (6) **IDCODE-revision honest correction**: per Gowin LittleBee Programming Manual Table 5-5, GW1N(R)-9 original = 0x1100581B, GW1N(R)-9C cost-down = 0x1100481B; both `set_device ... -device_version C` (build TCL) and `--device GW1NR-9C` (programmer_cli) required for ID code match. Inherited v0.3 contributions: Lean 4 refinement proof (OUKC.PhaseC.Dfumt8AluRefinement, 292 LOC, 0 sorry) establishes commutativity of the encode/abstract-op/decode square for all four unary operations + SELF⟲ primitive law + 7 algebraic laws. IBM Heron r2 per-op fidelity hierarchy NOP/ADIABATIC ≈ 0.977 > PHI ≈ 0.956 > NOT ≈ 0.912 > XOR ≈ 0.951 reflects gate-count-vs-noise correlation consistent with quantum-noise physics expectations. Honest scope: We do NOT claim 'world-first 8-valued quantum logic' — Shi et al. (MIT, 2026, arxiv:2506.09371) demonstrated d=8 Grover on a single trapped-ion qudit prior to this work; our distinction is 3-qubit basis encoding on transmon arrays vs single-system d=8 qudit. We do NOT claim 'first paraconsistent silicon' — PAL2v (Da Silva Filho 1998-; Abe & Nakamatsu 2009; de Carvalho Jr. 2025) realized in software libraries and microcontroller-level robotics. We do NOT claim 'first many-valued silicon' — Łukasiewicz/Belnap FPGAs date to 1990s. The to-our-knowledge novel quadruple is: (D1) the specific 8-tuple semantic mapping (Belnap FDE 4-value + 4 ontological extensions: INFINITY/ZERO/FLOWING/SELF), (D2) the SELF⟲ self-reflexive primitive realized as a hardware fixed point, (D3) the four-substrate cross-verification bound to a Lean 4 refinement specification, and (D4, new in v0.6) the chip-portability evidence across two Gowin silicon architectures. Three-party co-authorship per OUKC charter v1.0 (Nobuki Fujimoto / Rei / Claude). DRAFT v0.6 — feedback welcome via GitHub Discussions at fc0web/rei-aios.

Ruwei Huang, Xiaolong Tang, Junjie Wang, Xuezheng Qin

Polynomial multiplication serves as a fundamental computational primitive in modern cryptography–including fully homomorphic encryption and zero-knowledge proofs –as well as in digital signal processing. Its performance optimization has become increasingly critical amid the rapid development of privacy-preserving computation and blockchain technologies. To address the limitations of traditional algorithms in meeting the demands for high throughput and low latency, this study proposes a high-performance polynomial multiplication accelerator based on the collaborative optimization of GPU-NTT and the Karatsuba algorithm. The method deeply integrates the asymptotically optimal complexity of NTT with the constant-factor efficiency of Karatsuba at moderate scales, and fully exploits the parallel computing power of GPUs to construct a modular, multi-stage pipelined acceleration framework. The divide-and-conquer nature of the Karatsuba algorithm is leveraged for coarse-grained parallelism, splitting large polynomial multiplications into subproblems handled by GPU thread blocks in parallel, while each subproblem is solved with fine-grained parallelism using GPU-accelerated NTT kernels. An innovative zero-padding strategy is introduced to enhance the generality of the NTT kernels, and shared memory caching is employed to alleviate GPU memory bandwidth bottlenecks. Experimental results on the NVIDIA RTX 4060 GPU demonstrate that the proposed method achieves a stable speedup of 1.43 \(\times \) to 1.49 \(\times \) over the baseline GPU-NTT for lower-dimensional polynomials, and outperforms the KNTT algorithm by up to 2.44 \(\times \) for higher dimensions (e.g., \(\log _2 n = 14\) ), showing superior scalability and robustness. Kernel execution time analysis further confirms that the method benefits from efficient kernel fusion and balanced workload distribution, which effectively avoids pipeline stalls and ensures high-throughput execution. This research provides a significant performance optimization solution for the practical deployment of advanced cryptographic technologies such as FHE and ZKP.

Pengzhou He, Debapriya Basu Roy, Jiafeng Xie

No abstract is available for this record.

Jianming Tong, Jingtian Dang, Simon Langowski, Tianhao Huang · 9 authors

Zero-knowledge proof (ZKP) provers remain costly because multi-scalar multiplication (MSM) and number-theoretic transforms (NTTs) dominate runtime as they need significant computation. AI ASICs such as TPUs provide massive matrix throughput and SotA energy efficiency. We present MORPH, the first framework that reformulates ZKP kernels to match AI-ASIC execution. We introduce Big-T complexity, a hardware-aware complexity model that exposes heterogeneous bottlenecks and layout-transformation costs ignored by Big-O. Guided by this analysis, (1) at arithmetic level, MORPH develops an MXU-centric extended-RNS lazy reduction that converts high-precision modular arithmetic into dense low-precision GEMMs, eliminating all carry chains, and (2) at dataflow level, MORPH constructs a unified-sharding layout-stationary TPU Pippenger MSM and optimized 3/5-step NTT that avoid on-TPU shuffles to minimize costly memory reorganization. Implemented in JAX, MORPH enables TPUv6e8 to achieve up-to 10x higher throughput on NTT and comparable throughput on MSM than GZKP. Our code: https://github.com/EfficientPPML/MORPH.

S Jeon, Sungjin Park, Beomseok Kim, Juyoung Oh · 5 authors

No abstract is available for this record.

Ayumi Ohno, Kotaro Shimamura, Shinya Takamaeda-Yamazaki

Multi-Scalar Multiplication (MSM) is a primary computational bottleneck in modern cryptographic applications, especially zero-knowledge proofs. The Pippenger algorithm parallelizes MSM by decomposing it into numerous elliptic curve point additions (PADDs), but accelerating these operations on novel hardware like the Versal ACAP presents a significant challenge. This work explores the acceleration of PADDs on the Versal ACAP’s spatial array of 400 AI Engines (AIEs). While the SIMD-VLIW architecture of AIEs is ideal for the multiplication-heavy workloads in PADD, the complex 377-bit modular arithmetic, particularly carry propagation, demands architecture-aware optimization. We propose two key contributions: (1) algorithmic optimizations for carry propagation employing a carry-save-like technique to exploit VLIW and SIMD capabilities, and (2) a comparison of spatial mapping strategies and modular reduction algorithms to enhance intra- and intertask parallelism. Our approach achieves 567× speedup over the integrated CPU on the AIE evaluation board, utilizing 51.1% of the theoretical memory bandwidth.

Cheng Chen, Gangqiang Yang, Hongchao Zhou, Hailiang Xiong · 5 authors

Zero-Knowledge Proofs (ZKPs), particularly zk- SNARKs, are extensively employed in privacy-sensitive applications, but proof generation in such protocols imposes significant computational overhead. A major performance bottleneck is Multi-Scalar Multiplication (MSM), a highly compute-intensive operation on elliptic curves. While existing work focuses on specialized curves such as BLS12-377, which support more efficient elliptic curve arithmetic, there is limited exploration of MSM on general-purpose curves such as BLS12-381, which lack such optimizations and make parallelization more difficult. It faces the following challenges: imbalanced resource usage in modular multipliers, performance disparity between elliptic curve operations, and under-utilization of point addition unit in scheduling. To tackle these challenges, we propose FlexMSM, a flexible and scalable FPGA-based accelerator to accelerate MSM. FlexMSM innovates three techniques. First, we present a reconfigurable modular multiplier based on our proposed Hybrid-Weight Modular Multiplication algorithm, which strikes a balance between hardware cost and the number of MSM cores deployed on a single FPGA. Second, we propose a unified point addition scheme and design a fully pipelined point addition (PADD) unit. This design eliminates timing mismatch between pipeline stages and shortens the critical path. Third, we introduce dual-decoupled scheduling strategy for the bucket aggregation phase in Pippenger algorithm, which reduces pipeline stalls and improves the utilization of the PADD unit in MSM. To the best of our knowledge, FlexMSM is the first work to support up to double MSM cores for BLS12-381 curve on a single Xilinx UltraScale+ VU13P FPGA, leading to remarkable performance enhancements compared to existing works for input sizes from 218to 226. For the degree of 220, FlexMSM with two cores on a single FPGA achieves speedups of 19.29× over Hardcaml, 8.57× over if-ZKP, 2.14× over OPTIMSM on FPGA, 6.57× over ASIC-based work PipeZK, and 9.29× over GPU-based work GZKP.

Jiandong Zhang, Han Jiang, Chenkai Zeng, Qi Feng · 8 authors

Secure multiparty computation (MPC) over Z2kis more efficient than computations over fields, and studying MPC protocols under malicious security has practical application value. Malicious security with a dishonest majority over rings remains challenging. The most popular approach is SPDZ2k, however, this is a specific protocol that does not support the transformation of any existing semi-honest MPC protocols into malicious security protocols. The zero knowledge proof (ZKP)-based compiler satisfies this requirement. Existing state-of-the-art protocols have logarithmic online communication overhead in terms of the circuit size |C|, and their direct application to rings is nontrivial as they were originally designed for finite fields. In this work, we investigate the communication overhead to develop malicious security protocols. We bridge the gap between malicious security with abort and semi-honest security, by constructing a “GMW-style” verification protocol to achieve malicious security in a dishonest majority setting. This approach incurs a constant online communication overhead by enhancing the machinery of zero-knowledge fully linear interactive oracle proof (zk-FLIOP). Additionally, we extend the zk-FLIOP to work over any ring by invoking reverse multiplication friendly embeddings (RMFEs). Our results show that the online communication complexity of the verification process depends on only the security parameter, the number of parties, and the ring size. Furthermore, for small-scale circuits over Z2, we designed a distributed lookup table argument where both the total communication complexity and the computational cost are independent of the circuit size but of the input wires.

Elizaveta Pertseva, Valentin Robert, Clark Barrett, James Parker

Efforts to verify Zero-Knowledge Proof circuit encodings have highlighted the challenge of proving the correctness of quantifier-free statements that make use of both bitvector and finite field operations. Existing verification workflows are either manual or rely on SMT solvers, which scale poorly on some classes of problems for reasons that include difficulties with conversion operators and challenges reasoning about inequalities. To address these limitations, we present a novel Lean tactic BitModEq that leverages range lemmas and case analysis to produce verified translations from finite fields to bitvectors. Our approach, combined with bit-blasting, outperforms state-of-the-art SMT solvers, solving 19% more ZKP arithmetization benchmarks.

Mingshu Cong, Sherman S. M. Chow, Siu Ming Yiu, Tsz Hon Yuen

No abstract is available for this record.

José Ignacio Peinador Sala

A Modular DSP Architecture for Extreme-Precision Computation of π Author: José Ignacio Peinador SalaContact: joseignacio.peinador@gmail.comORCID: 0009-0008-1822-3452 🎯 TL;DR: What's This About? Problem: Calculating π at extreme precision hits a "Memory Wall" — parallel algorithms choke on shared memory access. Breakthrough: We discovered that π's calculation can be decomposed using modular arithmetic (mod 6), creating 6 independent computation channels with zero inter-thread communication. Key Insight: This decomposition is grounded in a formal isomorphism with polyphase filter banks in Digital Signal Processing (DSP), a bridge between number theory and engineering established in our companion work. Result: ✅ 100 million digits of π computed with just 6.8 GB RAM (95% parallelisation efficiency) ✅ Shared-Nothing architecture with strictly isolated memory per channel ✅ Stride-6 transition leaf with exact phase correction, compressing recursion depth by 2.6× ✅ Open-source implementation in Python/gmpy2, executable on Google Colab's free tier Why it matters: This architecture transforms an intrinsically memory-bound problem into a CPU-bound one, enabling near-linear scaling on commodity hardware without specialised HPC infrastructure. 📖 Executive Summary This repository hosts the reference implementation and experimental validation of the Hybrid Stride-6 architecture for extreme-precision computation of π. The architecture exploits the arithmetic structure of the Chudnovsky series by decomposing it into six independent modular channels, each processed by a dedicated worker with its own memory space. The decomposition is not an ad hoc optimisation but rests on a rigorous mathematical foundation: the polyphase isomorphism between modular arithmetic on ℤ/6ℤ and multirate signal processing. This isomorphism guarantees perfect reconstruction (no information loss across channels) and orthogonality (no inter-channel interference). The architecture is validated through the 100M Barrier Run: computing 10⁸ digits of π on a resource-constrained Google Colab instance (2 vCPUs, 12 GB RAM) in under 20 minutes, with 95% parallelisation efficiency and a sustained throughput of over 83,000 digits per second. 🏆 Key Contributions 🔬 Theoretical Foundations (Summarised from Companion Work) Polyphase Isomorphism: Formal proof that modular decomposition of integer-indexed series is equivalent to polyphase decimation in DSP Hexagonal Lattice Connection: Geometric motivation via the A₂ lattice (densest circle packing in the plane) Perfect Reconstruction Guarantee: Mathematical proof that the six channels recombine without aliasing or leakage ⚡ Computational Architecture Shared-Nothing Design: Six independent Python processes with strictly isolated memory spaces Stride-6 Transition Leaf: Processes blocks of 6 consecutive terms in a single operation, reducing recursion tree depth by log₂6 ≈ 2.585 Critical Phase Correction: Direct accumulation of the linear term B(k) prevents off-by-one-stride phase errors 📊 Experimental Validation 100M Barrier Run: 100 million digits computed on 12 GB RAM with 95% parallel efficiency Orthogonality Verification: ℓ² norm of channel terms matches norm of original series to machine precision Reference Comparison: All 10⁸ digits match y-cruncher reference values exactly 📈 Performance Highlights 🚀 "The 100M Barrier Run" — Extreme Validation Metric Result Significance Digits Calculated 100,000,000 Exascale-capable architecture Total Time 1,194.32 s (19.90 min) Sustained performance on cloud hardware Parallel Efficiency 95% (1.90× speedup) Near-linear scaling on 2 cores Peak RAM Usage ~6.8 GB Runs within 12 GB Colab limit Throughput 83,729 digits/second Competitive with optimised implementations Numerical Integrity Bit-exact match with y-cruncher Zero cumulative error 🏗️ Architectural Comparison Aspect Monolithic Binary Splitting Hybrid Stride-6 (This Work) y-cruncher (State-of-Art) Memory Pattern Contiguous, saturates bus Local per core, optimises cache Sequential disk I/O Parallel Model Fine-grained synchronisation Embarrassingly parallel (6 processes) Optimised with locks Scalability Memory-bound CPU-bound, linear to 6 cores Disk-speed limited RAM Requirement Entire dataset in memory Working set reduced 6× Uses disk as RAM Design Philosophy Maximise single-thread speed Maximise resource efficiency Maximise absolute speed 🚀 Quick Start & Reproduction 1. Instant Online Experiment (Recommended) Click above to run the complete experimental validation in Google Colab — no installation required! 2. Key Experiments to Reproduce The companion notebook provides step-by-step reproduction of all manuscript claims: Theoretical Foundation: Verify the polyphase decomposition and energy conservation Stride-6 Algorithm: Test parallel computation with arbitrary precision (100k digits) 100M Barrier Run: Reproduce the full-scale benchmark (requires ~7 GB RAM) Performance Analysis: Measure speedup and parallel efficiency ⚙️ Technical Implementation Details The "Stride-6" Computational Engine Unlike conventional Binary Splitting (processes terms individually), our engine implements a compressed transition leaf that calculates the aggregate effect of 6 consecutive terms: def stride6_leaf(k_start): """Calculate compressed transition for block [k, k+5]""" P, Q, B_acc = 1, 1, 0 for m in range(6): n = k_start + m P_n, Q_n, B_n = compute_chudnovsky_term(n) P *= P_n Q *= Q_n B_acc += B_n # Critical phase accumulation T_leaf = Q * B_acc # Correct phase synthesis return P, Q, T_leaf Key Innovation: Direct accumulation of the linear term B(n) prevents phase drift, preserving arithmetic integrity at any scale. Shared-Nothing Architecture Each of the 6 workers operates in complete memory isolation: Independent address spaces (no shared memory locks) Local garbage collection (prevents heap fragmentation) Cache-optimised access patterns (maximises L1/L2 utilisation) Numerical Stability Guarantees Orthogonal decomposition — zero information loss (verified experimentally) Arbitrary precision backend (gmpy2) with proven numerical stability Exact phase correction in the Stride-6 leaf 📚 Citation & Academic Use If this work contributes to your research, please cite: @article{peinador2026modularDSP, title={A Modular DSP Architecture for Extreme-Precision Computation of π}, author={Peinador Sala, José Ignacio}, journal={Zenodo}, year={2026}, doi = {10.5281/zenodo.17768718}, url = {https://github.com/NachoPeinador/Arquitectura-de-Hibridacion-Algoritmica-en-Z-6Z} } The companion theoretical work establishing the polyphase isomorphism is: @article{peinador2026polyphase, title={Polyphase Isomorphism between Modular Arithmetic and Multirate Signal Processing}, author={Peinador Sala, José Ignacio}, year={2026}, publisher={Zenodo}, doi = {10.5281/zenodo.17680023} } 🌐 The Broader Research Programme This architecture is one component of a larger investigation into the computational and physical consequences of the ℤ/6ℤ modular symmetry. Related projects include: Polyphase Isomorphism: Formal mathematical proof of the isomorphism between modular arithmetic and DSP. Modular Substrate Theory: Unified framework for cosmology and hadronic physics. Topological State Preparation: Quantum register initialisation and dissipative protection via ℤ/6ℤ superselection. Common Thread: All projects leverage modular arithmetic (ℤ/6ℤ) as a fundamental organising principle across mathematics, physics, and computation. ⚖️ Licensing & Usage ✅ Academic & Research Use (Free) Available under PolyForm Noncommercial License 1.0.0: Permitted: Academic research, teaching, personal projects, non-commercial forks Requirements: Attribution, license preservation, non-commercial use ⛔ Commercial Use (License Required) Commercial applications require explicit permission, including: Integration into proprietary software products Commercial hardware benchmarking services SaaS platforms and cloud computing services 💼 For Commercial Licensing Inquiries:Contact: joseignacio.peinador@gmail.comSubject: "Commercial License Inquiry — Modular π Architecture" 🌟 Acknowledgments This independent research was enabled by: Infrastructure & Tools Google Colab for democratised computational resources Python ecosystem (gmpy2, NumPy, SciPy, Jupyter) for scientific computing GitHub for open collaboration infrastructure Data & References y-cruncher for validation benchmarks Digital Signal Processing community for foundational theory Community & Inspiration The open-source scientific community for collective knowledge advancement Independent researchers worldwide pushing boundaries outside traditional institutions Last updated: June 2026 | Version: 3.0 | Status: Actively Maintained

Tarsha Kurdi, Mamone

We present ZK IR, a novel 32-bit instruction set architecture (ISA) specifically designed for efficient zero-knowledge proof generation using STARK protocols. Unlike existing zkVMs that adapt general-purpose ISAs like RISC-V, ZK IR is designed from first principles to minimize proving overhead while maintaining compatibility with modern compiler toolchains. Our key contribution is a rigorous analysis demonstrating that a pure 32-bit register architecture with software-based multi-precision arithmetic outperforms designs with wider registers or specialized field arithmetic units. We achieve approximately 2× reduction in constraint count compared to naive approaches. ZK IR uses the Baby Bear field (31-bit prime) with Plonky3 for proving, and provides an LLVM-based compiler infrastructure enabling developers to write ZK applications in Rust, C, and C++.

Yan Xu, Jingqi Zhang, Xiyan Dong, An Wang · 6 authors

Multi-scalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof protocols. To address this, we introduce FAMA, an FPGA-oriented MSM accelerator developed through algorithm-hardware co-optimization. By integrating a 3D-Pippenger optimization algorithm, FAMA minimizes computational complexity, while its compact dual-mode point addition (PADD) unit significantly reduces hardware overhead. Compared to the best CPU-based design, FAMA achieves over 184.20× speedup. It also outperforms state-of-the-art FPGA-based MSM accelerators, reducing resource overhead by more than 64% and boosting area-time product (ATP) by up to 37.09×.

Tong Wu, Niall Emmart, Oliver Diessel

Elliptic curve-based zero-knowledge proof (ZKP) protocols typically use multi-scalar multiplication (MSM) as a key primitive, making it one of the major performance bottlenecks in real-world ZK provers. In this paper, we present an FPGA-based MSM accelerator that achieved state-of-the-art performance in the 2023 ZPrize, a competition dedicated to advancing zero-knowledge cryptography, with submissions from both academia and industry. Our design achieves this through two primary innovations. First, we adopt affine (two-coordinate) representations for elliptic curve points, rather than resorting to projective coordinates, and leverage a batched inversion strategy to handle the expensive multiplicative inverse operation. Although many implementations extend points to projective form to avoid explicit inversions, they incur additional multiplications. By retaining affine coordinates and using the Montgomery trick (where multiple denominators are inverted at once), our accelerator reduces the overall number of real inversions per batch of point additions, drastically improving throughput while preserving a simpler coordinate system. Second, we introduce a novel hazard avoidance scheme that eliminates pipeline stalls arising from our high-latency elliptic curve addition pipeline. Through early detection and reordering of hazards, the pipeline remains fully utilized, thus maintaining continuous high throughput.

Daniel Escudero, Hong Cheng, H. M. Liu, Chaoping Xing · 5 authors

Reverse multiplication-friendly embeddings have played a crucial role in secure multiparty computation and zero-knowledge proofs. In this work, we generalize the notion of RMFEs todegree-DRMFEs. We present a general construction of degree-DRMFEs by generalizing the ideas on algebraic geometry used to construct traditional degree-2 RMFEs. Furthermore, our theory is given in a unified manner for general Galois rings, which include both rings of the form Zpkand fields like Fpk, which have been treated separately in prior works. We present multiple concrete sets of parameters for degree-DRMFEs (includingD= 2), which can be useful for future works. In the recent work of (Cheon & Lee, Eurocrypt’22), the concept of adegree-D packing methodwas formally introduced, which captures the idea of embedding multiple elements of a smaller ring into a larger ring. We show that the generalized notion of RMFEs todegree-D RMFEswhich, in spite of being “more algebraic” than packing methods, turn out to be essentially equivalent. Thus, our constructions of degree-DRMFEs are also degree-Dpacking methods.

Laura Atmanavičiūtė, Saulius Masteika

As privacy and security concerns increase, Zero Knowledge Proof (ZKP) technology offers a promising solution for secure digital verification. ZKP addresses key privacy and security challenges across individual, business, and public sectors by enabling data protection without revealing sensitive information. The aim of this study is to analyse ZKP’s application areas by reviewing current literature and case studies, examining its strengths, limitations, and potential risks. Findings highlight the capability of ZKP to enhance privacy, security, and verification processes across various fields, including blockchain technology, identity authentication, secure data sharing, and digital voting systems. The paper provides a balanced perspective on ZKP’s benefits and challenges, including computational complexity and scalability issues. By suggesting practical use cases, this work aims to contribute to a deeper understanding of how ZKP technology can support innovation across various industries while addressing critical privacy and security needs.

Thomas Haines, Rafieh Mosaheb, Johannes Müller, Reetika

Zero-Knowledge Proofs (ZKPs) are cryptographic building blocks of many privacy-preserving security protocols. An important research focus in this area is the development of post-quantum ZKPs. These are ZKPs whose security is reduced to computational hardness assumptions that are assumed to be intractable even by scalable quantum computers. In this paper, we study the post-quantum ZKPs of Jain, Krenn, Pietrzak, and Tentes (Asiacrypt 2012). These are the only ZKPs for proving arbitrary binary statements whose security reduces to the Learning Parity with Noise (LPN) problem-a very conservative post-quantum hardness assumption. We make the following contributions to further develop the potential and understanding of these ZKPs. First, we optimize the efficiency of the verifier by several orders of magnitude, making this part as computationally light as that of the prover. Second, we show that the only open source implementation of these ZKPs does not implement them correctly, allowing a malicious prover to convince the verifier of false statements. Third, we formally verify for the first time the security of these (optimized) ZKPs in EasyCrypt. Fourth, we show how these ZKPs can be used to construct the first code-based ZKP of shuffle and verifiable e- voting protocol.

Yasushi Takahashi, Naohisa Nishida, Yuji Unagami, Naoto Yanai

The recent machine learning requires huge machine resources and is often hard for users with limited resources. Although there are DPT, these are unsuitable for a situation where a trained model should be unrevealed from other users. In this paper, we first propose a new learning method, aggregated zero-knowledge deep learning (AZKDL), whereby even a user with a limited resource contributes to the learning process without revealing its model. Our main idea is to utilize aggregated zero-knowledge proofs where individual zero-knowledge proofs are aggregated into a single proof. Loosely speaking, users generate proofs for their training of parts of models and then aggregate both the models and the proofs to verify the entire models without revealing them. We also prove that AZKDL can detect malicious training. When we conduct experiments to evaluate AZKDL, we identify that even a client with the largest model parameters can finish the computation within a second. Furthermore, we propose the distributed proof-of-deep-learning (DPoDL) that rewards users who contribute to the learning process by applying AZKDL to a mining process of blockchains. DPoDL can detect malicious users by AZKDL.

Noel Elias

Efficiently verifying mathematical proofs and computations has been a heavily researched topic within Computer Science. Particularly, even repetitive steps within a proof become much more complex and inefficient to validate as proof sizes grow. To solve this problem, we suggest viewing it through the lens of Incrementally Verifiable Computation (IVC). However, many IVC methods, including the state-of-the-art Nova recursive SNARKs, require proofs to be linear and for each proof step to be identical. This paper proposes Lova, a novel framework to verify mathematical proofs end-to-end that solves these problems. Particularly, our approach achieves a few novelties alongside the first-of-its-kind implementation of Nova: (i) an innovative proof splicing mechanism to generate independent proof sequences, (ii) a system of linear algorithms to verify a variety of mathematical logic rules, and (iii) a novel multiplexing circuit allowing non-homogeneous proof sequences to be verified together in a single Nova proof. The resulting Lova pipeline has linear prover time, constant verifying capability, dynamic/easy modification, and optional zero-knowledge privacy to efficiently validate mathematical proofs. We offer potential use cases for Lova to secure entire Cyber-Physical Systems (CPS) pipelines, as well as localized CPS systems in automotive and healthcare devices. Code is available at https://github.com/noelkelias/lova.

Zhelei Zhou, Yun Li, Yuchen Wang, Zhaomin Yang · 8 authors

Homomorphic Encryption (HE) allows computations on encrypted data without decryption. It can be used where the users' information are to be processed by an untrustful server, and has been a popular choice in privacy-preserving applications. However, in order to obtain meaningful results, we have to assume an honest-but-curious server, i.e., it will faithfully follow what was asked to do. If the server is malicious, there is no guarantee that the computed result is correct. The notion of verifiable HE (vHE) is introduced to detect malicious server's behaviors, but current vHE schemes are either more than four orders of magnitude slower than the underlying HE operations (Atapoor et. al, CIC 2024) or fast but incompatible with server-side private inputs (Chatel et. al, CCS 2024). In this work, we propose a vHE framework ZHE: efficient Zero-Knowledge Proofs (ZKPs) that prove the correct execution of HE evaluations while protecting the server's private inputs. More precisely, we first design two new highly-efficient ZKPs for modulo operations and (Inverse) Number Theoretic Transforms (NTTs), two of the basic operations of HE evaluations. Then we build a customized ZKP for HE evaluations, which is scalable, enjoys a fast prover time and has a non-interactive online phase. Our ZKP is applicable to all Ring-LWE based HE schemes, such as BGV and CKKS. Finally, we implement our protocols for both BGV and CKKS and conduct extensive experiments on various HE workloads. Compared to the state-of-the-art works, both of our prover time and verifier time are improved; especially, our prover cost is only roughly 27–36× more expensive than the underlying HE operations, this is two to three orders of magnitude cheaper than state-of-the-arts.

Zhengbang Yang, Lutan Zhao, Peinan Li, Han Liu · 8 authors

Zero-knowledge proof (ZKP) allows a prover to convince a verifier of the truth of a statement without revealing any secret information. This property is utilized in numerous privacy-preserving applications. However, the huge overhead of proof generation impedes the widespread adoption of ZKP. As a result, many ZKP accelerators have been developed to speed up proof generation. However, existing accelerators are designed at the granularity of core operators and exhibit low hardware resource utilization and limited adaptability. In this paper, we identify the commonality of all computation stages in proof generation at the level of basic finite field arithmetic operations. Based on this insight, we propose LegoZK, a dynamically reconfigurable hardware accelerator for ZKP. LegoZK employs finite field arithmetic units (FAUs) as its fundamental components and integrates these FAUs with a hierarchical on-chip network (NoC). By dynamically configuring the FAUs and the NoC, LegoZK can effectively accelerate the entire proof generation process, achieving higher overall performance. Additionally, for the most time-consuming MSM, this paper proposes a fast, fully pipelined bucket reduction algorithm based on lookup tables, which significantly reduces the latency of MSM. Experimental results demonstrate that LegoZK achieves on average speedup of $31.96 \times$ and $11.30 \times$ in proof generation compared to the state-of-the-art ZKP ASIC accelerator PipeZK and the GPU accelerator GZKP, respectively. And compared to PipeZK, LegoZK achieves $\mathbf{5 0. 1 \%}$ area reduction and $\mathbf{3 7. 7 \%}$ power consumption reduction.

Nojan Sheybani, Anees Ahmed, Michel A. Kinsy, Farinaz Koushanfar

Zero-Knowledge Proofs (ZKPs) are a cryptographic primitive that allows a prover to demonstrate knowledge of a secret value to a verifier without revealing anything about the secret itself. ZKPs have shown to be an extremely powerful tool, as evidenced in both industry and academic settings. In recent years, the utilization of user data in practical applications has necessitated the rapid development of privacy-preserving techniques, including ZKPs. This has led to the creation of several robust open-source ZKP frameworks. However, there remains a significant gap in understanding the capabilities and real-world applications of these frameworks. Furthermore, identifying the most suitable frameworks for the developers' specific applications and settings is a challenge, given the variety of options available. The primary goal of our work is to lower the barrier to entry for understanding and building applications with open-source ZKP frameworks. In this work, we survey and evaluate 25 general-purpose, prominent ZKP frameworks. Recognizing that ZKPs have various constructions and underlying arithmetic schemes, our survey aims to provide a comprehensive overview of the ZKP landscape. These systems are assessed based on their usability and performance in SHA-256 and matrix multiplication experiments. Acknowledging that setting up a functional development environment can be challenging for these frameworks, we offer a fully open-source collection of Docker containers. These containers include a working development environment and are accompanied by documented code from our experiments. We conclude our work with a thorough analysis of the practical applications of ZKPs, recommendations for ZKP settings in different application scenarios, and a discussion on the future development of ZKP frameworks.