Blockchain Papers

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37 papersLast indexed Aug 31, 2026
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Jul 14, 2026·Zenodo (CERN European Organization for Nuclear Research)
0 cites
Theory, Framework, and Architecture: Hamilton V5

Karl Roesch

This paper formalizes the architecture of Hamilton V5, a continuous physical field transformer engineered for industrial automation. Moving beyond the discrete token-based processing of legacy models, Hamilton V5 introduces Always-On Autonomy (AOA), a paradigm that perpetually consumes raw spatiotemporal media inputs and maps them concurrently across a 12-dimensional mechanical phase space. To ensure structural stability and mitigate the compounding numerical drift common in autonomous systems, V5 integrates a closed-loop vector feedback correction mechanism. Crucially, the architecture secures high-speed hardware execution by implementing a Deterministic Proof-of-Stake Gate, which dynamically aborts actions if the predicted trajectory deviates by more than a threshold.

Open access
2 source records
Physical Unclonable Functions (PUFs) and Hardware Security
Embedded Systems Design Techniques
Network Time Synchronization Technologies
Original source
Mar 24, 2026·Zenodo (CERN European Organization for Nuclear Research)
0 cites
Universal Hardware-Level Intent Bus: An Architectural Paradigm for Proactive Contextual Synchronization in Mobile SoCs

VAITHYANATHAN, PRAKASH

Current mobile System-on-Chip (SoC) architectures suffer from a fundamental ”Reactive Polling Tax,” where high-level software must frequently interrupt low-power hardware states to query rawsensor telemetry. This paper introduces the Contextual Neural Bus (CNB), a dedicated, asynchronous hardware-level interconnect designed to shift context awareness from volatile software cycles to deterministic silicon logic. By utilizing a decentralized multi-modal fusion layer, the CNB generates Universal Intent Tokens (UITs)—64-bit cryptographic primitives that represent verified user states at the physical layer. Unlike legacy co-processors that merely buffer data, the CNB integrates a Hardware-Resident Zero-Knowledge Proof (ZKP) Generator to provide mathematical certainty of user intentwhile physically isolating raw biometric and environmental telemetry within a secure silicon enclave. Preliminary simulations using a digital-twin SoC model indicate a 90.8% reduction in interrupt driven power consumption, effectively achieving ”Energy-Neutral Privacy” by utilizing the resulting power surplus to offset cryptographic overhead. Furthermore, the architecture introduces Predictive L3 Cache Pre-warming, which anticipates user interactions to virtually eliminate ”cold-start” application latencies. By anchoring proactive computing in the deterministic reliability of silicon, this work establishes a scalable, privacy-first path toward zero-latency, energy-autonomous mobile ecosystems.

Open access
3 source records
Advanced Memory and Neural Computing
Interconnection Networks and Systems
Embedded Systems Design Techniques
Original source
Jan 1, 2026·Proceedings 2026 Network and Distributed System Security Symposium
0 cites
MEVisor: High-Throughput MEV Discovery in DEXs with GPU Parallelism

Weimin CHEN, Xiapu Luo

Decentralized finance (DeFi) is an emerging financial service on blockchain, enabling automatic and anonymous transactions.Within DeFi, decentralized exchanges (DEXs) maintain reserves of a pair of tokens and determine the exchange rate to swap tokens.However, DEXs also create opportunities for Maximal Extractable Value (MEV), where attackers include, exclude, or reorder DEX transactions to exploit price discrepancies of tokens and extract profit.Uncovering MEV opportunities requires high throughput, as the 12-second block interval and the vast search space impose strict time constraints.However, existing tools suffer from low throughput, as they rely on CPU-bound execution, which is hindered by frequent state forking and slow DEX execution.In this paper, we take the first step in leveraging GPU parallel computing power to boost MEV-search throughput in arbitrage and sandwich strategies.More precisely, we compile an MEV bot into a GPU application and then launch thousands of GPU threads to search for profit in parallel.To this end, we design new solutions to address three major challenges: designing cheatcodes to simulate transactions on GPU, proposing a memory manager to reduce GPU memory usage, and designing strategyaware mutations to improve input diversity.We implement a prototype named MeVisor that runs DEXs on GPUs and searches for MEV using a parallel genetic algorithm.Evaluated on 3,941 real MEV cases from Ethereum, MeVisor achieves 3.3M-5.1Mtransactions per second, outperforming the CPU baseline by 100,000x.In a large-scale study of Q1 2025 data, MeVisor estimates MEV opportunities ranging from 2 to 14 transactions, yielding at most $1.1 million in MEV profit.

Open access
Parallel Computing and Optimization Techniques
Embedded Systems Design Techniques
Advanced Neural Network Applications
Original source
Oct 1, 2025·Electronics
1 cites
Systematic HLS Co-Design: Achieving Scalable and Fully-Pipelined NTT Acceleration on FPGAs

Jinfa Hong, Bohao Zhang, Gaoyu Mao, Patrick S. Y. Hung · 5 authors

Lattice-based cryptography (LBC) is an essential direction in the fields of homomorphic encryption (HE), zero-knowledge proofs (ZK), and post-quantum cryptography (PQC), while number theoretic transformations (NTT) are a performance bottleneck that affects the promotion and deployment of LBC applications. Field-programmable gate arrays (FPGAs) are an ideal platform for accelerating NTT due to their reconfigurability and parallel capabilities. High-level synthesis (HLS) can shorten the FPGA development cycle, but for algorithms such as NTT, the synthesizer struggles to handle the inherent memory dependencies, often resulting in suboptimal synthesis outcomes for direct designs. This paper proposes a systematic HLS co-design to progressively guide the synthesis of NTT accelerators. The approach integrates several key techniques: arithmetic module resource optimization, conflict-free butterfly scheduling, memory partitioning, and template-based automated design fusion. It reveals how to resolve pipeline bottlenecks in HLS-based designs and expand parallel processing, guiding microarchitecture iterations to achieve an efficient design space. Compared to existing HLS-based designs, the area-latency product achieves a performance improvement of 1.93 to 191 times, and compared to existing HDL-based designs, the area-cycle product achieves a performance improvement of 1.7 to 10.6 times.

Open access
Embedded Systems Design Techniques
Analog and Mixed-Signal Circuit Design
Experimental Learning in Engineering
Original source
Sep 9, 2025·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 cites
Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm–Hardware Co-Design

Yan Xu, Jingqi Zhang, Xiyan Dong, An Wang · 6 authors

Multi-scalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof protocols. To address this, we introduce FAMA, an FPGA-oriented MSM accelerator developed through algorithm-hardware co-optimization. By integrating a 3D-Pippenger optimization algorithm, FAMA minimizes computational complexity, while its compact dual-mode point addition (PADD) unit significantly reduces hardware overhead. Compared to the best CPU-based design, FAMA achieves over 184.20× speedup. It also outperforms state-of-the-art FPGA-based MSM accelerators, reducing resource overhead by more than 64% and boosting area-time product (ATP) by up to 37.09×.

Embedded Systems Design Techniques
Numerical Methods and Algorithms
Low-power high-performance VLSI design
Original source
Jul 24, 2025·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
1 cites
FPGA-Based Hardware Accelerator of zk-SNARK

Baoze Zhao, Conghui Luo, Wenjin Huang, Yihua Huang

Zero-Knowledge Proof (ZKP) has gained widespread application across various domains, demonstrating remarkable success. Among ZKP algorithms, Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (zk-SNARK) is the most widely used. However, despite its advantages of small proof size and succinct verification, zk-SNARK proof generation faces significant challenges due to high computational demands, limiting its practical application. This paper addresses these challenges by accelerating two computationally intensive operations in zk-SNARK proof generation, Number Theory Transformation (NTT) and Multi-Scalar Multiplication (MSM), using FPGAs. In the implementation of NTT hardware accelerators for zk-SNARK applications, the traditional 4-step algorithm often encounters conflicts between off-chip bandwidth and on-chip memory. To resolve this issue, we propose an innovative approach that enhances accelerator performance by recursively applying the 4-step algorithm to create a more efficient 6-step algorithm. For MSM hardware acceleration on FPGAs, existing works are often constrained by limited on-chip memory, restricting the use of longer slice lengths, which are crucial for higher performance when using the commenly used Pippenger algorithm. To overcome this limitation, we introduce the Batch Method, optimizing off-chip memory consumption, enabling the accelerator to use longer slice lengths and achieve superior performance. Experimental results demonstrate that the proposed NTT design achieves 1.76× higher DSP efficiency than the SAM. Meanwhile, the proposed MSM design demonstrates 1.24× higher performance than the MSMAC with aligned frequency and number of PEs. When benchmarked against the GPU implementation GZKP, our MSM design exhibits 1.16× and 1.46× higher performance than GZKP for BLS12-381 and BN-254, respectively. However, the NTT design remains at a disadvantage due to the bandwidth limitation between our platform, Xilinx Alveo U250, and GZKP’s platforms, Nvidia GTX 1080 Ti and Nvidia Tesla V100.

Embedded Systems and FPGA Design
Embedded Systems and FPGA Applications
Embedded Systems Design Techniques
Original source
May 17, 2025·International Journal of Current Science Research and Review
1 cites
Web Assembly and Blockchain for High-Performance Secure Front-End Systems

Yuliia Horbenko

Web Assembly (Wasm) and blockchain technology offer a viable solution for reliable and high-performance front-end systems. Wasm provides high execution speeds by incorporating code from high-level languages to improvise on performance limitations. Its sand-boxed execution model enhances security by extenuating memory-related weaknesses. Similarly, blockchain reinforces security with decentralized, tamper-resistant data structures and smart contracts. Conventional blockchain frameworks often suffer from computational overhead, but Wasm-based execution platforms like Polkadot and EOS optimize resource utilization and improve interoperability. This integration facilitates high-speed, reliable interactions in decentralized applications (dApps). Potential benefits include fast and secure off-chain computations, hence reducing blockchain congestion in front-end frameworks. However, challenges remain in securing Wasm execution in decentralized environments and optimizing blockchain and Wasm interoperability. A promising direction is to exploit Just-In-Time (JIT), Ahead-of-Time (AOT) compilation schemes along with zero-knowledge proofs to further enhance performance and security characteristics. By coupling Wasm’s efficiency with blockchain’s security, scalable and decentralized front-end systems are evolving to meet challenging web demand scenarios.

Open access
Real-Time Systems Scheduling
Security and Verification in Computing
Embedded Systems Design Techniques
Original source
Apr 25, 2025·INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT
0 cites
Toward Transparent and Modular DApps: A Web3 SaaS Prototype for Token Lifecycle Management

Priyanshu P. Wadke

Abstract- The evolution of blockchain and Web3 technologies has paved the way for decentralized application platforms that enable transparent, tamper-proof transactions without relying on centralized servers. However, existing solutions such as Gitcoin and Giveth are either too complex or unsuitable for modular deployment in educational and lightweight environments. This paper proposes MetaSuite, a role-based, blockchain-driven Software-as-a-Service (SaaS) platform that enables users to create, transfer, and donate tokens while allowing an administrator to securely withdraw funds. Built entirely on the Ethereum blockchain using Solidity smart contracts, MetaSuite operates without a backend and integrates wallet-based authentication via MetaMask and Ethers.js. The platform ensures transparent fund management through on-chain event logging and role-based access controls. Performance evaluations on the Ethereum HoleskyTestnet demonstrate the system’s reliability, gas-efficiency, and real-time responsiveness. By eliminating backend dependencies and emphasizing traceability, MetaSuite serves as a minimalistic yet scalable Web3 solution suitable for academic, experimental, and small-scale real-world deployments. Keywords—Blockchain, Web3, Smart Contracts, Ethereum, MetaMask, Tokenization, SaaS, Ethers.js, Decentralized Applications.

Open access
Software Engineering Techniques and Practices
Embedded Systems Design Techniques
Software Testing and Debugging Techniques
Original source
Mar 22, 2025·SoutheastCon 2025
1 cites
Exploring Hedera Hashgraph for Efficient Data Transfer in MOOS-IvP Aquaticus Testbed

Adarsh Bharadwaj, J.R. James, Michael Novitzky

The Hedera hashgraph algorithm has been shown to be Asynchronous Byzantine Fault Tolerant (ABFT) for achieving consensus on adding a transaction into local copies of a hash-graph distributed database. The ABFT result is theoretically the best result that can be achieved for distributed ledger technology (DLT) regarding trusting that the data in each local copy of a distributed global database has not been tampered with during each transaction process to add data into the global distributed database. The hashgraph algorithm ensures that each transaction in each local copy of the global database can be trusted to be a true copy of the data submitted by each node in the set of peer nodes as long as no more than 1/3 of the peer nodes in the peer-to-peer network of hashgraph nodes have been compromised. The Aquaticus, capture the flag (CTF) force-on-force free-play competition between Artificial Intelligence (AI)/Machine Learning (ML) agents enables use of a variety of ML algorithms to build AI/ML agents to play and win the CTF game in a maritime environment by employing the MOOS-IvP autonomy stack. This paper explores the integration of Hedera hashgraph DLT into the MOOS-IvP Aquaticus testbed for efficient and secure data transfer in collaborative autonomy scenarios. The study focuses on developing a multi-node Hedera network to support decentralized, real-time, and tamper-proof communication among autonomous agents in adversarial maritime environments. A detailed network setup using Docker and solo-compose is outlined, including transitioning from single-node to multi-node configurations. The system's application is evaluated in the context of the Aquaticus capture-the-flag (CTF) environment, highlighting its role in synchronizing flag positions and tagging status among unmanned surface vehicles (USVs), Initial findings indicate that the Hedera network can enhance data integrity and scalability while reducing latency in distributed systems. Challenges in scaling and resource optimization are discussed, along with proposed future work to deploy physical nodes using Raspberry Pi and integrate reinforcement learning frameworks like PyQuaticus. This research provides a foundation for advancing decentralized communication in autonomous robotics, emphasizing its potential for secure and robust multi-agent collaboration.

Embedded Systems Design Techniques
Advanced Data Storage Technologies
Modular Robots and Swarm Intelligence
Original source
Mar 4, 2025·IACR Transactions on Cryptographic Hardware and Embedded Systems
3 cites
SimdMSM: SIMD-accelerated Multi-Scalar Multiplication Framework for zkSNARKs

Rui Jiang, Cong Peng, Min Luo, Rongmao Chen · 5 authors

Multi-scalar multiplication (MSM) is the primary building block in many pairing-based zero-knowledge proof (ZKP) systems. MSM at large scales has become the main bottleneck in ZKP implementations. Inspired by existing SIMD-accelerated work, we are focused on accelerating MSM computing efficiency using SIMD instructions in a single CPU environment. First, we propose a SIMD-accelerated MSM computing architecture with no write conflicts and constant memory overheads. This architecture utilizes multithreading to achieve task-level and loop-level parallelism and employs a three-tier buffer mechanism to maximize the utilization of the SIMD engine. Instanced with AVX512-IFMA instructions, we implement six SIMD elliptic curve arithmetic engines for different point addition in three coordinate systems and two groups. Moreover, we integrate our AVX-MSM implementation into the libsnark library, naming it AVX-ZK. In more detail, point deduplication and “Three-Stage” memory optimization are proposed to address problems existing in practical applications. Based on the RELIC library, our performance results on the BLS12-381 curve show that our AVX-MSM achieves up to 27.86x speedup over the most popular Pippenger algorithm. Compared with libsnark, our AVX-ZK implementation achieves over 11.53x (up to 20.26x) speedup under standard benchmarks.

Open access
Parallel Computing and Optimization Techniques
Distributed and Parallel Computing Systems
Embedded Systems Design Techniques
Original source
Dec 11, 2024·2024 International Conference on Sustainable Communication Networks and Application (ICSCNA)
0 cites
Customizable Component-Based Application Assembly with Storage Algorithm

A Suganya, P Nagarasu, Shankar Siva, M. Vignesh

AegisLibre is a novel decentralized storage algorithm designed to prioritize high security and efficiency for sensitive data like personal information, text, photos, and other private content. Drawing inspiration from blockchain technology, it combines dynamic encryption, smart contracts, zero-knowledge proofs (ZKP), and Proof of Storage (PoS) to offer a highly secure and verifiable storage system. This paper explores the foundations of AegisLibre, compares it with existing algorithms such as IPFS, discusses its key features, and presents an analysis of its security capabilities and performance.

Scheduling and Optimization Algorithms
Embedded Systems Design Techniques
Advanced Manufacturing and Logistics Optimization
Original source
Nov 15, 2024·Wiley
0 cites
Design-Centric Parameter-Based Architecture for End-to-End Consensus

Ravi Kanth Kotha, Susmita Mandal, Tene Ramakrishnudu

Implementation of cross-enterprise business processes is complex. The globalization of businesses has resulted in a greater demand for business platforms that provide information security and privacy. In these processes, technological advancements are extensively leveraging automation and simplification. However, most enterprise systems are still centralized and work in silos. The advent of Distributed Ledger Technologies (DLT) and Smart Contracts is addressing some security and privacy challenges. However, these systems do not provide a perfect balance between end-to-end and cross-enterprise visibility and security. A further challenge is that the consensus/agreement provided by these systems cannot accommodate wider application requirements. The business platforms currently provide agreement at the level of individual messages without considering the context of the business workflow. This paper defines the Design-Centric Consensus (DCC) and information flow security inspired by the literature on information flow models and security protocols. It also identifies the need for multiple levels of consensus based on the application requirements. An architectural framework is also proposed that provides application-specific consensus while maintaining DCC and visibility

Distributed systems and fault tolerance
Systems Engineering Methodologies and Applications
Embedded Systems Design Techniques
Original source
Oct 11, 2024·arXiv (Cornell University)
0 cites
SoK: Verifiable Cross-Silo FL

Aleksei Korneev, Jan Ramon

Federated Learning (FL) is a widespread approach that allows training machine learning (ML) models with data distributed across multiple devices. In cross-silo FL, which often appears in domains like healthcare or finance, the number of participants is moderate, and each party typically represents a well-known organization. For instance, in medicine data owners are often hospitals or data hubs which are well-established entities. However, malicious parties may still attempt to disturb the training procedure in order to obtain certain benefits, for example, a biased result or a reduction in computational load. While one can easily detect a malicious agent when data used for training is public, the problem becomes much more acute when it is necessary to maintain the privacy of the training dataset. To address this issue, there is recently growing interest in developing verifiable protocols, where one can check that parties do not deviate from the training procedure and perform computations correctly. In this paper, we present a systematization of knowledge on verifiable cross-silo FL. We analyze various protocols, fit them in a taxonomy, and compare their efficiency and threat models. We also analyze Zero-Knowledge Proof (ZKP) schemes and discuss how their overall cost in a FL context can be minimized. Lastly, we identify research gaps and discuss potential directions for future scientific work.

Open access
2 source records
cs.LG
cs.AI
cs.CR
Original source
Oct 4, 2024·arXiv (Cornell University)
0 cites
Research Directions for Verifiable Crypto-Physically Secure TEEs

Sylvain Bellemare

A niche corner of the Web3 world is increasingly making use of hardware-based Trusted Execution Environments (TEEs) to build decentralized infrastructure. One of the motivations to use TEEs is to go beyond the current performance limitations of cryptography-based alternatives such as zero-knowledge proofs (ZKP), fully homomorphic encryption (FHE), and multi-party computation (MPC). Despite their appealing advantages, current TEEs suffer from serious limitations as they are not secure against physical attacks, and their attestation mechanism is rooted in the chip manufacturer's trust. As a result, Web3 applications have to rely on cloud infrastruture to act as trusted guardians of hardware-based TEEs and have to accept to trust chip manufacturers. This work aims at exploring how we could potentially architect and implement chips that would be secure against physical attacks and would not require putting trust in chip manufacturers. One goal of this work is to motivate the Web3 movement to acknowledge and leverage the substantial amount of relevant hardware research that already exists. In brief, a combination of: (1) physical unclonable functions (PUFs) to secure the root-of-trust; (2) masking and redundancy techniques to secure computations; (3) open source hardware and imaging techniques to verify that a chip matches its expected design; can help move towards attesting that a given TEE can be trusted without the need to trust a cloud provider and a chip manufacturer.

Open access
2 source records
cs.CR
cs.AR
cs.ET
Original source
Jul 17, 2024·Future Internet
9 cites
NFT Technology for Enhanced Global Digital Registers: A Novel Approach to Tokenization

Alexandr Kuznetsov, Emanuele Frontoni, Alexandr Kuznetsov, Ruslan Shevchuk · 5 authors

In the rapidly evolving field of digital asset management, centralized and decentralized global registries have become essential tools for organizing, tracking, and distributing digital assets. However, existing systems often face challenges regarding security, censorship resistance, interoperability, customizability, and scalability. This research paper aims to address these gaps by proposing a novel decentralized global registry system based on blockchain technology and non-fungible tokens (NFTs). The research paper makes several key contributions to the field of digital asset management. First, it provides a detailed system design for the proposed decentralized global registry, outlining its architectural components, functional modules, and integration with blockchain and NFT technologies. Second, it offers a thorough comparative analysis of the advantages and limitations of the proposed system in relation to existing centralized and decentralized registries. Finally, the paper presents potential use cases and practical applications of the proposed system in various industries, demonstrating its versatility and adaptability to different contexts and requirements. In conclusion, this research paper contributes significantly to the ongoing efforts to improve digital asset management by presenting a novel, decentralized global registry system based on blockchain technology and NFTs. The proposed system addresses the key limitations of existing solutions and offers a promising direction for future research and development in this critical field.

Open access
Embedded Systems Design Techniques
VLSI and FPGA Design Techniques
Advanced Data Storage Technologies
Original source
Jul 9, 2024·ACM Transactions on Embedded Computing Systems
5 cites
LiteHash: Hash Functions for Resource-Constrained Hardware

Sagar Dev Achar, P Thejaswini, Sukumar Nandi, Sunit Kumar Nandi

The global paradigm shift toward edge computing has led to a growing demand for efficient integrity verification. Hash functions are one-way algorithms which act as a zero-knowledge proof of a datum’s contents. However, it is infeasible to compute hashes on devices with limited processing power and memory. Hence, we propose four novel LiteHash functions which are architecturally similar to SHA-512 yet simpler. By using various approximation techniques, our implementations reduce the computational costs of digesting a message into a hash. On validating our proposed designs using the NIST PRNG Test Suite, we observe SHA-512 equivalent cryptographic security while satisfying all desired hash function property requirements. We observe a minimum of 9.41% reduction in area, 20.47% reduction in power, and 22.05% increase in throughput. Our designs offer a throughput of up to 2 Gbps while reducing area and power by a maximum of 16.86% and 32.48%, respectively. LiteHash functions also support the computation of the entire SHA-2 family of hash functions (SHA-224/256/384/512) with minor architectural modifications.

Physical Unclonable Functions (PUFs) and Hardware Security
Security and Verification in Computing
Embedded Systems Design Techniques
Original source
Jun 27, 2024·IEEE Transactions on Network Science and Engineering
10 cites
EPoW: Energy-Efficient Proof-of-Work

Shasha Yu, Yanan Qiao, Junge Bo, Fan Yang · 5 authors

Proof-of-Work (PoW) is a consensus mechanism widely applied in blockchain applications such as Bitcoin and Ethereum. In PoW, only the first miner solving the PoW puzzle by Hash Collisions wins the reward. Thus, PoW-powered cryptocurrencies have become increasingly energy inefficient due to the fierce competition among the participants. Additionally, PoW can cause centralization in blockchain networks. To address these challenges, this research proposes an incentive mechanism named EPoW. EPoW has been proven to generally benefit the conservation of energy in Bitcoin mining by giving miners no incentive to devote a higher hash rate. Moreover, EPoW is an instrument for decentralization by discouraging the collusion among miners. Then, a dual security verification mechanism is proposed to enhance the security of blockchain networks. Finally, extensive comparative experiments are conducted to validate the effectiveness of EPoW in energy efficiency. The research indicates that EPoW eliminates the miner's incentive to devote a higher hash-rate than all their counterparts, thus relieving the malignant competition and conserving expensive energy. Additionally, EPoW alleviates the problem of centralization caused by mining pools.

Low-power high-performance VLSI design
Parallel Computing and Optimization Techniques
Embedded Systems Design Techniques
Original source
May 19, 2024·2024 IEEE Symposium on Security and Privacy (SP)
10 cites
Chronos: Finding Timeout Bugs in Practical Distributed Systems by Deep-Priority Fuzzing with Transient Delay

Yuanliang Chen, Fuchen Ma, Yuanhang Zhou, Ming Gu · 6 authors

Delays are inevitable in complex distributed environments. Timeout mechanisms are commonly used to handle unexpected failures in distributed systems. However, incorrect timeout handling or implementation errors in timeout mechanisms can lead to system hang-ups or crashes. Such timeout bugs may be crucial and pose a significant threat to the availability and security of distributed systems.In this work, we introduce Chronos, a general testing framework for automatically detecting timeout bugs in distributed systems with deep-priority transient delays. First, we propose general runtime delayed libraries that dynamically inject fine-grained delays in a Distributed System Under Test (DSUT). To effectively trigger delays and constantly explore timeout bugs in deep paths, Chronos harnesses a deep-priority guided fuzzing that dynamically generates high-quality delay sequences in the runtime. Then, Chronos utilizes transient delays to eliminate the time overhead caused by actual delays and accelerate the test process. We implemented and evaluated Chronos on four widely used distributed systems, including ZooKeeper, MySQL-Cluster, HDFS, and Go-Ethereum. Compared with the state-of-the-art techniques, Random, Brute-Force, and Coverage-Guided fault injection, Chronos covers 26.40%, 21.69%, and 15.14% more timeout mechanism logic, respectively. Furthermore, Chronos has detected 27 timeout bugs in these real-world applications, which have been repaired by the corresponding maintainers.

Software Testing and Debugging Techniques
Embedded Systems Design Techniques
Parallel Computing and Optimization Techniques
Original source
Dec 12, 2023·2023 International Conference on Field Programmable Technology (ICFPT)
15 cites
BSTMSM: A High-Performance FPGA-based Multi-Scalar Multiplication Hardware Accelerator

Baoze Zhao, Wenjin Huang, Tianrui Li, Yihua Huang

Zero-knowledge Proof (ZKP) is widely used in applications like online auctions and electronic voting to ensure privacy. Among ZKP algorithms, Zero-Knowledge Succinct NonInteractive Argument of Knowledge (zk-SNARK) stands out for its efficiency in generating concise proofs and reducing verification costs. However, the generation of zk-SNARK proofs poses challenges due to computation overhead and time requirements, hindering practical applications. Multi-Scalar Multiplication (MSM) is a computationally intensive step in zk-SNARK proof generation and has become a focus for industry acceleration efforts. In this paper, we introduce Barrel State Tracking MSM (BSTMSM), a high-performance FPGA-based MSM hardware accelerator. Unlike traditional approaches, BSTMSM focuses on tracking the state of each barrel rather than the pipeline of point addition (PADD) circuits. This approach eliminates the impact of barrel collisions and improves the utilization rate of PADD circuits by enabling the utilization of the associative law of addition. Furthermore, we have successfully implemented up to double PADD circuits in BSTMSM, leading to remarkable performance enhancements compared to other existing works. For an input size of $2^{20}$, BSTMSM outperforms the ASIC-based work PipeZK by $ 1.53\times$. For an input size of $2^{26}$, BSTMSM achieves performance improvements of $ 2.22\times$ compared to the FPGA-based work HARDCAML and $ 1.24\times$ compared to the GPU-based work GZKP.

Parallel Computing and Optimization Techniques
Low-power high-performance VLSI design
Embedded Systems Design Techniques
Original source
Dec 1, 2023·2023 IEEE Third International Conference on Signal, Control and Communication (SCC)
2 cites
Plug-and-Play MARL for SoC and Power Balance Regulation of Heterogeneous BESSs

Mudhafar Al-Saadi, Michael Short

Intelligent management of power flow and storage balance has proven its worth in supporting economic, sustainable operation of microgrids powered mainly by intermittent renewable energy resources. In particular, the introduction of Multi-Agent Reinforcement Learning (MARL) to solve power management and storage balance problems has been very successful. MARL primary-secondary control was the subject of a recent application in solving power storage flow problems in battery-based micro- and smart-grids, focusing upon vehicle-to-grid applications under realistic environmental considerations such as infrastructural influences. Such influences can worsen the accuracy of plug-and-play batteries' charge-discharge synchronization and hence control stabilization, power flow balance, batteries' health/life, and energy efficiency. This paper proposes a solution to this issue in a DC autonomous microgrid with multiple, heterogeneous batteries. Multiagent-neighbor-to-neighbor information is exploited to enhance the real-time balance of the load participation, and a real-time decentralized infrastructure compensation and power flow organization consumption/loss is established to compensate for infrastructural/environmental influence on the control. Moreover, implementation in a real-time economic sustainable participation policy on each BESS in a test microgrid is explored. The results verify improved synchronization of the batteries’ power flow with reduced plug-and-play time by (4.16%), enhanced output voltage balance by (2.76-8%), reduced power consumption by (1.908-2.94%), improved power flow balance by (2.765-6.486%), and better power flow efficiency by (0.9196-2.626%) when compared to a baseline MARL implementation.

Semiconductor Lasers and Optical Devices
Embedded Systems Design Techniques
Semiconductor materials and devices
Original source