Exploration of Algorithms for the Hardware Acceleration of Multi-Scalar Multiplication on FPGA

Abstract

In this paper, we present the exploration of algorithms for the hardware acceleration of multi-scalar multiplication (MSM) on field programmable gate arrays (FPGAs). We have aggregated Verilog and System Verilog implementations of popular algorithms for each component in the MSM processing stack, including large integer multiplication, modular reduction, and elliptic curve point addition, doubling, and scalar multiplication. Additionally, we have compared these algorithms in the context of MSM and evaluated their performance. Our results highlight the efficiency of application specific hardware over general purpose processors for computationally intensive operations. Our contribution provides a valuable resource for those interested in using hardware acceleration to improve the efficiency of zero knowledge proof systems.