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October 1, 2017· 2017 IEEE International High Level Design Validation and Test Workshop (HLDVT)
conference-paper

Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study

Authors:Zhongqi ChengTim SchmidtGuantao LiuRainer Doomer

Abstract

The rapidly growing design complexity has become a big obstacle and dramatically increased the time required for SystemC simulation. In this case study, we exploit different levels of parallelism, including thread- and data-level parallelism, to accelerate the simulation of a Bitcoin miner model in SystemC. Our experiments are performed on two multi-core processors and one many-core Intel(g) Xeon PhiTMCoprocessor. Our results show that with the combination of data- and thread-level parallelism, the peak simulation speed improves by over 11x on a 4-core host, 50x on a 16-core host, and 510x on a 60-core host, respectively. The results confirm the efficiency of combining thread- and datalevel parallelism for higher SystemC simulation speed, and can serve as a benchmark for future optimization of system level design, modeling, and simulation.

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